The present invention generally relates to semiconductor processing, and in particular to a system for regulating post exposure bake time and temperature.
The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips), typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit may be formed on a single wafer. One such step is referred to as a post exposure bake step, which follows a masking step.
The masking step is used to protect one area of the wafer while working on another area. This process is referred to as photolithography or photo-masking. A photo resist, or light-sensitive film, is applied to the wafer, giving it characteristics similar to a piece of photographic paper. Depending on the resist system, post exposure baking may be employed to reduce standing wave effects and/or to thermally catalyze chemical reactions that amplify a latent image. Post exposure baking has been shown to increase linewidth control and resolution. Conventionally, post exposure baking times and/or temperatures have been pre-calculated and/or based on indirect measurements (e.g., concentration of chemicals in vapor retrieved from post exposure bake chamber). Such pre-calculated control parameters and/or indirect measurements may not, therefore, account for wafer to wafer variations, variations within a wafer and/or apparatus idiosyncrasies, for example.
In an etching step, the wafer is then xe2x80x9cdevelopedxe2x80x9d (the exposed photo resist is removed) and baked to harden the remaining photo resist pattern. The temperature at which the wafer is baked, and the period of time for which it is baked affect the critical dimensions of the wafer. The wafer is then exposed to a chemical solution or plasma (gas discharge) so that areas not covered by the hardened photo resist are etched away. The photo resist is removed using additional chemicals or plasma and the wafer is then inspected to ensure the image transfer from the mask to the top layer is correct.
Due to the extremely fine patterns that are exposed on the photo resist, controlling the post exposure bake temperature and the time period over which one or more temperatures are applied during the post exposure bake are significant factors in achieving desired critical dimensions. It has been demonstrated that the post-exposure bake step is important in IC manufacture since it can be employed to activate chemical reactions that catalyze the amplification of an initial UV-light induced latent image. Within-wafer and/or wafer-to-wafer variations during post-exposure bake will contribute significantly to linewidth variation. Thus, maintaining the post exposure bake at a desired temperature, for a desired period of time, may enable uniformity in photo resist hardening and increase the quality of the underlying integrated circuit being manufactured. Small changes in the time and temperature history of the post exposure bake can substantially alter photo resist hardening, resulting in lack of image line control. For example, a few degrees temperature difference and/or an overly long or short post exposure bake time can drastically affect critical dimensions.
To keep processing times under control, sensitive photo resists are employed. A typical highly sensitive photo resist is a chemically amplified photo resist. A chemically amplified photo resist is one in which exposure to actinic radiation produces a catalyst for a reaction that alters the solubility of the resist. A common example is a positive tone resist containing a photo acid generator that generates an acid catalyst on exposure to actinic radiation. The photo-generated acid may catalyze a deprotection reaction that increases the solubility of the photo resist in an aqueous base.
A post exposure baking (PEB) step can be employed to cause the photo-generated catalyst to diffuse and react within the photo resist coating. The PEB step has a significant effect on the quality of pattern transfer. If the PEB step is too long, or if the resist is overheated, then the catalyst can migrate outside of the exposed portion of the resist into surrounding unexposed areas. If the PEB step is too short or the resist is under heated, diffusion and reaction of the catalyst may be unduly limited resulting in an inadequate solubility contrast between exposed and unexposed regions of the photo resist. Time and temperature are related in the post exposure bake process. For example, higher temperatures may cause faster baking and subsequently faster hardening, while lower temperatures may cause slower baking and correspondingly slower hardening. Ideally, all portions of a wafer would bake and harden at precisely the same rate when subjected to identical temperatures for identical times. Unfortunately, such uniform baking and hardening does not always occur, with different wafer portions baking and hardening at different rates. For example, the center of a wafer may bake and harden at a different rate than the edge of a wafer. Thus, an efficient system and/or method to monitor the post exposure bake and hardening process, and to control post exposure baking time and temperature, is desired to increase fidelity in image transfer.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is not intended to identify key/critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides a system that facilitates controlling post exposure baking temperature and the time over which post-exposure baking temperatures are applied. An exemplary system may employ one or more light sources arranged to project light onto one or more lines and/or gratings on a wafer and one or more light sensing devices (e.g., photo detector, photodiode) for detecting light reflected by, and/or allowed to pass through, the one or more lines and/or gratings. The light reflected from, and/or passing through, the one or more gratings is indicative of at least one parameter of the post exposure bake process (e.g., percent completion of hardening, desired critical dimensions) that may vary in correlation with post exposure baking time and temperature.
In conventional systems, heating and chilling apparatus may be employed to control the temperature within a post exposure bake chamber. But such conventional systems may only monitor the temperature in the chamber and/or of the wafer as a whole, with such temperatures being employed in evaluating adherence to pre-calculated times and temperatures. The present invention provides for one or more temperature controlling components arranged to correspond to a particular wafer portion. The temperature controlling components may be, for example, heat lamps, baking plates, and/or fluid conducting apparatus. It is to be appreciated by one skilled in the art that any suitable temperature controlling component can be employed with the present invention. Each temperature controlling component may be responsible for heating and/or cooling one or more particular wafer portions. The temperature controlling components are selectively driven by the system to produce temperatures on a wafer portion at a desired level for a desired time based on data collected from in situ linewidth and/or grating measurements being employed to produce feedback information operable to control the temperature controlling components. The baking and hardening progress is monitored by the system by comparing the size and/or shape of the lines and/or gratings on the wafer to desired size and/or shapes. As a result, more optimal baking and hardening is achieved by controlling the temperatures applied to the portions of the wafer by feedback generated from direct measurements, which in turn increases fidelity of image transfer.
One particular aspect of the invention relates to a system for regulating post exposure baking time and temperature. At least one temperature controlling component operates to heat and/or cool a portion of a wafer, and a temperature controlling component driving system drives the at least one temperature controlling component. A system for directing light directs light to one or more lines and/or gratings being baked and hardened on the wafer, and a measuring system measures critical dimensions of the one or more lines and/or gratings based on light reflected, and/or passed through, the lines and/or gratings. A processor is operatively coupled to the measuring system and a temperature controlling component driving system. The processor receives critical dimension data from the measuring system, and the processor uses the data to at least partially base control of the at least one temperature controlling component so as to regulate temperature of the at least one portion of the wafer being developed.
Another aspect of the present invention relates to a method for regulating post exposure baking temperature. The method includes defining a wafer as one or more portions and baking and hardening one or more lines and/or gratings on a wafer. While the lines and/or gratings are being baked and hardened, the method involves directing light onto at least one of the lines and/or gratings, collecting light reflected by and/or passed through the at least one grating and analyzing the reflected and/or passed through light to determine the progress of baking and hardening of the wafer and the acceptability of the critical dimensions being achieved. The method further includes generating feedback information that can be employed to control a temperature controlling component to regulate the temperature of the at least one portion.